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tgthr

Something about syntax......

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I have some problems compling with c2c-plus compiler.

Now I'm programming for PIC16C74B.

 

First, following sentence,

 

#define IsManual()  (((PORTD)&00001000b)>>3) //manual, auto

 

I just want to change "IsManual()" to the rightmost term of that sentence.

But compiling error occurs. When I change "IsManual()" to "IsManual"(erasing parentheses), then error disappears. What is wrong?

 

 

Second, I got compiling error message like

 

"Undefined identifier 'TRISD'"

 

I think some of the register files in pic16c74 are not defined by default.

How can I solve this problem? Do I have to specify all the register file addresses manually?

Are there any easier way to solve this problem?

And What register files are defined by default?

 

 

 

Please Reply.

Have a NICE day~

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I believe macro functionality is limited.

 

You can't have a macro with an argument list.

So the brakets cause an error.

 

 

:)

But, I don't pass any parameters to the macro. I just want to change "IsManual()" to "XXXXXX".

Just brackets in macro can cause that problem??

 

And...Would you let me know all predefined register (and their addresses)files when the target is pic16c74b? I think some register files are already defined and some are not. It's confusing. That make me even doubting about addresses of predefined register files.

Please save me in this confusion.

Help~

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Only some register are defined embebded in C2C

you must read Help file C2C, in my case I wrote

a customised header file to picmicro about work

like this:

 

// HEADER FILE

// PIC16F870

// Modificado para trabajar con el C2C v 4.1.6e

// Daniel O. Vaccaro - Octubre del 2002

 

#ifndef _16F877

 

#define _16F877

 

char PORTC   @ 7;

char PORTD   @ 8;

char PORTE   @ 9;

 

char PIR1    @ 12;

char PIR2    @ 13;

char TMR1L   @ 14;

char TMR1H   @ 15;

char T1CON   @ 16;

char TMR2    @ 17;

char T2CON   @ 18;

char SSPBUF  @ 19;

char SSPCON  @ 20;

char CCPR1L  @ 21;

char CCPR1H  @ 22;

char CCP1CON @ 23;

char RCSTA   @ 24;

char TXREG   @ 25;

char RCREG   @ 26;

char CCPR2L  @ 27;

char CCPR2H  @ 28;

char CCP2CON @ 29;

char ADRESH  @ 30;

char ADCON0  @ 31;

 

char TRISC   @ 0x87;

char TRISD   @ 0x88;

char TRISE   @ 0x89;

 

char PIE1    @ 0x8C;

char PIE2    @ 0x8D;

char PCON    @ 0x8E;

 

char SSPCON2 @ 0x91;

char PR2     @ 0x92;

char SSPADD  @ 0x93;

char SSPSTAT @ 0x94;

 

char TXSTA   @ 0x98;

char SPBRG   @ 0x99;

 

char ADRESL  @ 0x9E;

char ADCON1  @ 0x9F;

 

char EE_DATA  @ 0x10C;

char EE_ADR   @ 0x10D;

char EEDATH  @ 0x10E;

char EEADRH  @ 0x10F;

 

char EE_CON1  @ 0x18C;

char EE_CON2  @ 0x18D;

 

 

//#pragma bit  PEIE    @ 11.6  mapped_into_all_banks

 

/*

Los valores definidos solamente por su nombre son Mascaras y

los valores precedidos por _BIT indican la posicion del bit

*/

 

#define  T0IF        4

#define  T0IF_BIT    2

#define  INTF        2

#define  INTF_BIT    1

#define  RBIF        1

#define  RBIF_BIT    0

 

#define  T0IE_BIT    5

#define  GIE_BIT     7

 

// PIR1

#define  TMR1IF 1

#define  TMR1IF_BIT 0

#define  TMR2IF 2

#define  TMR2IF_BIT 1

#define  CCP1IF 4

#define  CCP1IF_BIT 2

#define  TXIF        16

#define  TXIF_BIT   4

#define  RCIF   32

#define  RCIF_BIT   5

#define  ADIF   64

#define  ADIF_BIT   6

 

// PIR2

#define  EEIF        8

 

// TICON

#define  TMR1ON 1

#define  TMR1ON_BIT 0

#define  TMR1CS 2

#define  TMR1CS_BIT 1

#define  T1SYNC_ 4

#define  T1SYNC_BIT 2

#define  T1OSCEN 8

#define  T1OSCEN_BIT 3

#define  T1CKPS0 16

#define  T1CKPS0_BIT 4

#define  T1CKPS1 32

#define  T1CKPS1_BIT 5

 

// T2CON

#define  T2CKPS0     1

#define  T2CKPS1     2

#define  TMR2ON      4

#define  TOUTPS0     8

#define  TOUTPS1     16

#define  TOUTPS2     32

#define  TOUTPS3     64

 

// CCP1CON

#define  CCP1M0      1

#define  CCP1M1      2

#define  CCP1M2      4

#define  CCP1M3      8

#define  CCP1Y       16

#define  CCP1X       32

 

// RCSTA

#define  RX9D   1

#define  RX9D_BIT   0

#define  OERR   2

#define  OERR_BIT   1

#define  FERR   4

#define  FERR_BIT   2

#define  ADDEN       8

#define  ADDEN_BIT 3

#define  CREN   16

#define  CREN_BIT   4

#define  SREN   32

#define  SREN_BIT   5

#define  RX9         64

#define  RX9_BIT     6

#define  SPEN        128

#define  SPEN_BIT   7

 

// ADCON0

#define  ADON   1

#define  ADON_BIT   0

#define  GO          4

#define  GO_BIT 2

#define  CHS0   8

#define  CHS0_BIT   3

#define  CHS1   16

#define  CHS1_BIT   4

#define  CHS2   32

#define  CHS2_BIT   5

#define  ADCS0       64

#define  ADCS0_BIT 6

#define  ADCS1       128

#define  ADCS1_BIT 7

 

// PIE1

//#define  TMR1IE  1

//#define  TMR2IE  2

//#define  CCP1IE  4

#define  TXIE       16

#define  TXIE_BIT   4

#define  RCIE       32

#define  RCIE_BIT   5

#define  ADIE       64

#define  ADIE_BIT   6

 

// PCON

#define  BOR_    1

#define  POR_    2

 

// TXSTA

#define  TX9D   1

#define  TX9D_BIT   0

#define  TRMT   2

#define  TRMT_BIT   1

#define  BRGH   4

#define  BRGH_BIT   2

#define  SYNC   16

#define  SYNC_BIT   4

#define  TXEN   32

#define  TXEN_BIT   5

#define  TX9         64

#define  TX9_BIT     6

#define  CSRC   128

#define  CSRC_BIT   7

 

// ADCON1

#define  PCFG0       1

#define  PCFG0_BIT 0

#define  PCFG1       2

#define  PCFG1_BIT 1

#define  PCFG2       4

#define  PCFG2_BIT 2

#define  PCFG3       8

#define  PCFG3_BIT 3

#define  ADFM        128

#define  ADFM_BIT  7

 

// EEDATA

#define  RD          1

#define  RD_BIT 0

#define  WR          2

#define  WR_BIT 1

#define  WREN        4

#define  WREN_BIT   2

#define  WRERR       8

#define  WRERR_BIT 3

#define  EEPGD       128

#define  EEPGD_BIT 7

 

#endif

 

I hope help

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