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What Value Do I Load Onto Tmr0 ?

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Hi cac,

I thought you would have solved the problem and infact i was very anxiously waiting for your reponse.

My reasoning turned out to be right. ie. it take 3 clock cycles for the timer0 to start running. 1st clock cycle to write onto tmr0 and another 2 clock cycles of inhibition after the write operation.

I changed the code to tmr0+=0; and tried it on the mplab sim with a stop watch.

But when i set the break point & made it run, it did not stop. I didn't know why.

So i made another variable by name check initialized to 0 & added  to it. ie.

tmr0+=check; & checked it up. I got 259,518,1036,1295,1554... some times i got +- one cycle but got corrected the next run.


I found one more thing, writing tmr0 value to tmr0 itself causes 4 cycles dealy.ie.

tmr0=tmr0;. I got 260,520,780,1041,1300,1559,1820....

The instruction "tmr0 += 0;" does not generate any code so there is not place for a break point.


Using "tmr0 = tmr0 + 0;" generates code but it does not generate the "ADDWF TMR0,F" that is required.


So I use inline asm to generate the required code:



movlw 0

addwf _tmr0,F



It's possible that the BoostC code generator may introduce some quirky behavior when trying to get the specific machine code to use TMR0 for this way.




I believe you are correct that one additional TMR0 clock is lost during the instruction execution.


Something like you posted a little while back.


I think the TMR0 is clocked during phase 3 of the instruction execution, at the same time as the modify part of a read-modify-write instruction executes.


When the ADDWF TMR0,F executes:


The instruction cycle executes in 4 phases:

ADDWF opcde is decoded in phase 1.

TMR0 value moved to ALU register in phase 2 .

Add W to ALU register in phase 3.

ALU register is written to TMR0 in phase 4.


Note: The ALU register is internal to the PIC and is used by the Arithmetic Logic Unit to hold a temporary operand for an math or logic operation.


After the write in phase 4 it takes two more instruction cycles before TMR0 starts counting.



Edited by cac001

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