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RSABear

Demo Code & Proposed Pic12f675.h File

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Hi Guys,

 

I had some troubles with the tiny 12F675 this weekend. In order to help others and get my program going I wrote some test routines on the good old Velleman K8048 board again. You can include in your samples and have a look at the one-liner in the include file.

 

//////////////////////////////////////////////////////////////////
//
// Demo Code For Velleman K8048 Programmer/Experimentation Board
//
// Author: RSABear
// Target Device: PIC12F675
// Clock Frequency: 4MHz
//

#include <system.h>

// Set the device configuration bits
// 4.0Mhz Internal oscillator, you can't use the crystal for the 8 PIN devices on the K8048
#pragma DATA _CONFIG, _CPD_OFF & _CP_OFF  & _WDT_OFF & _BODEN_OFF & _PWRTE_ON  & _MCLRE_OFF & _INTRC_OSC_NOCLKOUT

// Should you "loose" your OSCCAL value you can replace it with the following line of code
// This requires an updated PIC12F675.h file with the _OSCCAL definition
// You also need to use Progpic2.exe to program the PIC - see notes on Velleman users Forum
// e.g. for 0x3440 you would enter:
//#pragma DATA _OSCCAL, 0x3440

// Tell the compiler the device clock frequency to get the correct delays generated
#pragma CLOCK_FREQ	4000000

// Some logic defintions
#define SET 	1
#define TRUE 	1
#define CLEAR 	0
#define RESET 	0
#define FALSE 	0
#define ZERO 	0
#define ON 		1
#define OFF 	0

// Page 11 of the K8048 user manual
#define LD1 	GPIO2
#define LD2 	GPIO4
#define SW1 	GPIO5

unsigned char i_count, i_state;

void main()
{
// Get and set the 12F629/675 OSSCAL value
asm  //Load Factory Calibration Value Into OSCCAL
{
	bsf _status,RP0 
	call 0x3FF
	movwf _osccal 
	bcf _status,RP0
}

// Some of the following register settings are not required for this demo
// They are included to provide you with a framework for future use

// 12F675 register settings
vrcon = CLEAR;					// Turn off the voltage reference peripheral
cmcon = 0b00000111; 			// Disble comparator module - make Port A digital I/O port
ansel = CLEAR;					// For the 12F675 Only
gpio = CLEAR;					// Clear the output ports
trisio = 0b00101000;	   // Make GP05 Input (GPIO3 is always input)
wpu = 0b00000000;				// En/disable Weak Pull Ups

//		Bit 7   - NOT GPPU: GPIO Pull-up Enable
//		Bit 6   - INTEDG: Interrupt Edge Select
//		Bit 5   - TMR0 Clock Source Select 0 = Internal instruction cycle clock (CLKOUT)
//		Bit 4   - TMR0 Source Edge Select (not used)
//		Bit 3   - 1 = PSA to timer0
//		Bit 2-0 - 101 = Prescaler set to divide by 32
option_reg = 0b01000100;

//		Bit 7   - Unimplemented: Read as ‘0’
//		Bit 6   - 0 = Timer1 is on
//		Bit 5-4 - 00 = divide by 1 
//		Bit 3   - 0 = LP oscillator is off
//		Bit 2	- 1 = Do not synchronize external clock input
//		Bit 1	- 0 = Internal clock (FOSC/4)
//		Bit 0	- 1 = Enables Timer1
t1con = 0b00000101;

// Enable/disbale interrupts
clear_bit(intcon, T0IE);			// Disable Timer 0 Interrupts
clear_bit(intcon, GIE);				// Disable Global Interrupts

// Flash LD1 10 times
for (i_count = 1; i_count < 10; i_count++) 
	{
		delay_ms(50);
		toggle_bit(gpio, LD1);
		delay_ms(50);
	}

// Flash LD2 10 times
for (i_count = 1; i_count < 10; i_count++) 
	{
		delay_ms(50);
		toggle_bit(gpio, LD2);
		delay_ms(50);
	}

// Switch LD1 & 2 Off
gpio = 0b00000000;			// Clear the output ports

// Initialise the program variables
i_state = 0x00;
i_count = 0x00;

  while(TRUE) {


	// SW1 - "STATE" button is pressed
	if ( test_bit(gpio, SW1) > OFF)  {			// When the switch is pressed the code will enter the IF

		while ( test_bit(gpio, SW1) > OFF)	 	// Wait until the switch is released
			{
				set_bit(gpio, LD1);					// User entertainment - show the switch press
				set_bit(gpio, LD2);
				delay_ms(10);							// Wait - simple switch debouce
				}

			// Cycle through the states
			// 00 - Flash LD1
			// 01 - Flash LD2
			// 02 - Flash LD1 & 2
			// 03 - LD1 & LD2 Off
			i_state = ( i_state < 0x03 ) ? ++i_state : CLEAR;

	}	// End SW1 if


	// Do something with the i_state
	switch ( i_state )
		{
		case 0x00:	// Flash LD1
			toggle_bit(gpio, LD1);
			clear_bit(gpio, LD2);
			delay_ms(80);
			break;
		case 0x01:	// Flash LD2
			toggle_bit(gpio, LD2);
			clear_bit(gpio, LD1);
			delay_ms(80);
			break;
		case 0x02:	// Flash LD1 & LD2
			toggle_bit(gpio, LD1);
			toggle_bit(gpio, LD2);
			delay_ms(80);
			break;
		case 0x03:	// LD1 & LD2 Off
			clear_bit(gpio, LD1);
			clear_bit(gpio, LD2);
			break;
		} // End Switch

} // End while Loop

} // End main()

 

The proposed PIC12F675 include file:

 

// ***************************************
// BoostC Header file for PIC12F675
// Author(s): David Hobday
//
// Copyright (C) 2003-2007 Pavel Baranov
// Copyright (C) 2003-2007 David Hobday
// All Rights Reserved
// ***************************************


////////////////////////////////////////////////////////////////////////////
//
//	   Register Definitions
//
////////////////////////////////////////////////////////////////////////////

#define W					 0x0000 
#define F					 0x0001 

/////// Register Files//////////////////////////////////////////////////////
#define INDF				  0x0000 
#define TMR0				  0x0001 
#define PCL				   0x0002 
#define STATUS				0x0003 
#define FSR				   0x0004 
#define GPIO				  0x0005 
#define PCLATH				0x000A 
#define INTCON				0x000B 
#define PIR1				  0x000C 
#define TMR1L				 0x000E 
#define TMR1H				 0x000F 
#define T1CON				 0x0010 
#define CMCON				 0x0019 
#define ADRESH				0x001E 
#define ADCON0				0x001F 
#define OPTION_REG			0x0081 
#define TRISIO				0x0085 
#define PIE1				  0x008C 
#define PCON				  0x008E 
#define OSCCAL				0x0090 
#define WPU				   0x0095 
#define IOC				   0x0096 
#define IOCB				  0x0096 
#define VRCON				 0x0099 
#define EEDATA				0x009A 
#define EEDAT				 0x009A 
#define EEADR				 0x009B 
#define EECON1				0x009C 
#define EECON2				0x009D 
#define ADRESL				0x009E 
#define ANSEL				 0x009F 

/////// STATUS Bits ////////////////////////////////////////////////////////
#define IRP				   0x0007 
#define RP1				   0x0006 
#define RP0				   0x0005 
#define NOT_TO				0x0004 
#define NOT_PD				0x0003 
#define Z					 0x0002 
#define DC					0x0001 
#define C					 0x0000 

/////// GPIO Bits ////////////////////////////////////////////////////////
#define GP5				   0x0005 
#define GPIO5				 0x0005 
#define GP4				   0x0004 
#define GPIO4				 0x0004 
#define GP3				   0x0003 
#define GPIO3				 0x0003 
#define GP2				   0x0002 
#define GPIO2				 0x0002 
#define GP1				   0x0001 
#define GPIO1				 0x0001 
#define GP0				   0x0000 
#define GPIO0				 0x0000 

/////// INTCON Bits ////////////////////////////////////////////////////////
#define GIE				   0x0007 
#define PEIE				  0x0006 
#define T0IE				  0x0005 
#define INTE				  0x0004 
#define GPIE				  0x0003 
#define T0IF				  0x0002 
#define INTF				  0x0001 
#define GPIF				  0x0000 

/////// PIR1 Bits //////////////////////////////////////////////////////////
#define EEIF				  0x0007 
#define ADIF				  0x0006 
#define CMIF				  0x0003 
#define T1IF				  0x0000 
#define TMR1IF				0x0000 

/////// T1CON Bits /////////////////////////////////////////////////////////
#define TMR1GE				0x0006 
#define T1CKPS1			   0x0005 
#define T1CKPS0			   0x0004 
#define T1OSCEN			   0x0003 
#define NOT_T1SYNC			0x0002 
#define TMR1CS				0x0001 
#define TMR1ON				0x0000 

/////// COMCON Bits ////////////////////////////////////////////////////////
#define COUT				  0x0006 
#define CINV				  0x0004 
#define CIS				   0x0003 
#define CM2				   0x0002 
#define CM1				   0x0001 
#define CM0				   0x0000 

/////// ADCON0 Bits ////////////////////////////////////////////////////////
#define ADFM				  0x0007 
#define VCFG				  0x0006 
#define CHS1				  0x0003 
#define CHS0				  0x0002 
#define GO					0x0001 
#define NOT_DONE			  0x0001 
#define GO_DONE			   0x0001 
#define ADON				  0x0000 

/////// OPTION Bits ////////////////////////////////////////////////////////
#define NOT_GPPU			  0x0007 
#define INTEDG				0x0006 
#define T0CS				  0x0005 
#define T0SE				  0x0004 
#define PSA				   0x0003 
#define PS2				   0x0002 
#define PS1				   0x0001 
#define PS0				   0x0000 

/////// PIE1 Bits //////////////////////////////////////////////////////////
#define EEIE				  0x0007 
#define ADIE				  0x0006 
#define CMIE				  0x0003 
#define T1IE				  0x0000 
#define TMR1IE				0x0000 

/////// PCON Bits //////////////////////////////////////////////////////////
#define NOT_POR			   0x0001 
#define NOT_BOD			   0x0000 

/////// OSCCAL Bits ////////////////////////////////////////////////////////
#define CAL5				  0x0007 
#define CAL4				  0x0006 
#define CAL3				  0x0005 
#define CAL2				  0x0004 
#define CAL1				  0x0003 
#define CAL0				  0x0002 

/////// IOCB Bits ////////////////////////////////////////////////////////
#define IOCB5				 0x0005 
#define IOCB4				 0x0004 
#define IOCB3				 0x0003 
#define IOCB2				 0x0002 
#define IOCB1				 0x0001 
#define IOCB0				 0x0000 

/////// IOC Bits ////////////////////////////////////////////////////////
#define IOC5				  0x0005 
#define IOC4				  0x0004 
#define IOC3				  0x0003 
#define IOC2				  0x0002 
#define IOC1				  0x0001 
#define IOC0				  0x0000 

/////// VRCON Bits /////////////////////////////////////////////////////////
#define VREN				  0x0007 
#define VRR				   0x0005 
#define VR3				   0x0003 
#define VR2				   0x0002 
#define VR1				   0x0001 
#define VR0				   0x0000 

/////// EECON1 Bits ////////////////////////////////////////////////////////
#define WRERR				 0x0003 
#define WREN				  0x0002 
#define WR					0x0001 
#define RD					0x0000 

/////// ANSEL Bits /////////////////////////////////////////////////////////
#define ADCS2				 0x0006 
#define ADCS1				 0x0005 
#define ADCS0				 0x0004 
#define ANS3				  0x0003 
#define ANS2				  0x0002 
#define ANS1				  0x0001 
#define ANS0				  0x0000 

////////////////////////////////////////////////////////////////////////////
//
//	   Configuration Bits
//
////////////////////////////////////////////////////////////////////////////

#define _CPD_ON			   0x3EFF 
#define _CPD_OFF			  0x3FFF 
#define _CP_ON				0x3F7F 
#define _CP_OFF			   0x3FFF 
#define _BODEN_ON			 0x3FFF 
#define _BODEN_OFF			0x3FBF 
#define _MCLRE_ON			 0x3FFF 
#define _MCLRE_OFF			0x3FDF 
#define _PWRTE_OFF			0x3FFF 
#define _PWRTE_ON			 0x3FEF 
#define _WDT_ON			   0x3FFF 
#define _WDT_OFF			  0x3FF7 
#define _LP_OSC			   0x3FF8 
#define _XT_OSC			   0x3FF9 
#define _HS_OSC			   0x3FFA 
#define _EC_OSC			   0x3FFB 
#define _INTRC_OSC_NOCLKOUT   0x3FFC 
#define _INTRC_OSC_CLKOUT	 0x3FFD 
#define _EXTRC_OSC_NOCLKOUT   0x3FFE 
#define _EXTRC_OSC_CLKOUT	 0x3FFF 

/////////////////////////////////////////////////
// Config Register
/////////////////////////////////////////////////
#define _CONFIG			   0x2007

/////////////////////////////////////////////////
// OSCCAL Register
/////////////////////////////////////////////////
#define _OSCCAL			   0x03FF

/////////////////////////////////////////////////
// EEPROM Base Address when programing
/////////////////////////////////////////////////
// To initialise EEPROM when a device is programmed
// use #pragma DATA _EEPROM, 12, 34, 56 
#define _EEPROM			   0x2100

volatile char indf				   @INDF;
volatile char tmr0				   @TMR0;
volatile char pcl					@PCL;
volatile char status				 @STATUS;
volatile char fsr					@FSR;
volatile char gpio				   @GPIO;
volatile char pclath				 @PCLATH;
volatile char intcon				 @INTCON;
volatile char pir1				   @PIR1;
volatile char tmr1l				  @TMR1L;
volatile char tmr1h				  @TMR1H;
volatile char t1con				  @T1CON;
volatile char cmcon				  @CMCON;
volatile char adresh				 @ADRESH;
volatile char adcon0				 @ADCON0;
volatile char option_reg			 @OPTION_REG;
volatile char trisio				 @TRISIO;
volatile char pie1				   @PIE1;
volatile char pcon				   @PCON;
volatile char osccal				 @OSCCAL;
volatile char wpu					@WPU;
volatile char ioc					@IOC;
volatile char iocb				   @IOCB;
volatile char vrcon				  @VRCON;
volatile char eedata				 @EEDATA;
volatile char eeadr				  @EEADR;
volatile char eecon1				 @EECON1;
volatile char eecon2				 @EECON2;
volatile char adresl				 @ADRESL;
volatile char ansel				  @ANSEL;

 

Regards

RSABear

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