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I've tried using #pragma DATA to set various configuration bits, but it always ends up crashing ezdownloader.exe (brings up the "send error report window" )

 

Here's an example i just tried: #pragma DATA _CONFIG2H, _WDT_OFF_2H

 

Trying to disable the WDT but failing...

Edited by toolrocket

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Anybody have any words about changing configuration bits with the ezdownloader? The boostc manual makes it look pretty straightforward. Everything compiles ok, but crashes on download.

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It may not be possible to alter configuration words from the bootloader context.

 

Are you sure that your PIC is able to change configuration words while a program is running?

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It may not be possible to alter configuration words from the bootloader context.

 

Are you sure that your PIC is able to change configuration words while a program is running?

 

In fact i'm sure it's not. I was hoping somebody had a work-around?

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It may not be possible to alter configuration words from the bootloader context.

 

Are you sure that your PIC is able to change configuration words while a program is running?

 

In fact i'm sure it's not. I was hoping somebody had a work-around?

Yes you can't change the configuration word. The only way to do this would be to blow away the bootloader and overwrite the whole of program memory. You can do this if you use ICD2 or some other programming device.

 

Regards

Dave

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So what are the configuration bits set to then Dave ?

 

Does EZ Controller data sheet tell those with these controllers what they are.

 

Reynard

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The .h files in the sourceboost\include directory have definitions of all the configuration bits. They did a really good job with that.

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Yes, but what are they set to when the bootloader was installed ?

 

Watchdog ON or watchdog OFF etc.

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Yes, but what are they set to when the bootloader was installed ?

 

Easy controller congifuration (PIC18F252):

;************************************************************
; MCU DIRECTIVES
;************************************************************
__CONFIG	_CONFIG1H, _OSCS_OFF_1H & _HS_OSC_1H  
__CONFIG	_CONFIG2L, _BOR_ON_2L & _BORV_27_2L & _PWRT_ON_2L
__CONFIG	_CONFIG2H, _WDT_OFF_2H & _WDTPS_128_2H
__CONFIG	_CONFIG4L, _STVR_ON_4L & _LVP_OFF_4L & _DEBUG_OFF_4L 
__CONFIG _CONFIG5H, _CPB_ON_5H
__CONFIG _CONFIG6H, _WRTB_ON_6H & _WRTC_ON_6H
__CONFIG _CONFIG7H, _EBTRB_ON_7H

 

Easy controller turbo congifuration (PIC18F2520):

;************************************************************
; MCU DIRECTIVES
;************************************************************
; HS OSC, No fails safe clock monitor (would use internal clock if external failed, disable internal external clock switchover
; for 20MHz Clock
; __CONFIG	_CONFIG1H, _OSC_HS_1H & _FCMEN_OFF_1H & _IESO_OFF_1H
; for 4 x 10MHz Clock
__CONFIG	_CONFIG1H, _OSC_HSPLL_1H & _FCMEN_OFF_1H & _IESO_OFF_1H

; Enable power up reset timer, Brown out enabled and controlled by software, brown out reset if slight dip
__CONFIG	_CONFIG2L, _PWRT_ON_2L & _BOREN_ON_2L & _BORV_0_2L

; Watchdog off, prescaler set to 128
__CONFIG	_CONFIG2H, _WDT_OFF_2H & _WDTPS_128_2H

; MCLR pin enabled, timer1 hi-power (more noise immune), 
; PORTB default to digital I/O (for compatibility as PIC18F252 has no analogue mode on thses pins)
; CCP2 input/output is multiplexed with RC1
__CONFIG	_CONFIG3H, _MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_PORTC_3H

; Stack full/underflow will cause Reset, Single-Supply ICSP disabled, 
; Instruction set extension and Indexed Addressing mode disabled (Legacy mode),
; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
__CONFIG	_CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _XINST_OFF_4L & _DEBUG_OFF_4L

; Block 0 (000800-001FFFh) not code-protected
; Block 1 (002000-003FFFh) not code-protected
; Block 2 (004000-005FFFh) not code-protected
; Block 3 (006000-007FFFh) not code-protected
__CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L

; Boot block (000000-0007FFh) code-protected
; Data EEPROM not code-protected
__CONFIG _CONFIG5H, _CPB_ON_5H & _CPD_OFF_5H

; Block 0 (000800-001FFFh) not write-protected
; Block 1 (002000-003FFFh) not write-protected
; Block 2 (004000-005FFFh) not write-protected
; Block 3 (006000-007FFFh) not write-protected
__CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L

  ; Boot block (000000-0007FFh) write-protected
  ; Configuration registers (300000-3000FFh) write-protected
  ; Data EEPROM not write-protected
__CONFIG _CONFIG6H, _WRTB_ON_6H & _WRTC_ON_6H & _WRTD_OFF_6H

  ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
  ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
  ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
  ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
__CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L

; Boot block (000000-0007FFh) protected from table reads executed in other blocks
__CONFIG _CONFIG7H, _EBTRB_ON_7H

 

Regards

Dave

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